module dds_sine_interface
(
input clk,rst_n,
input avs_wr_n,
input [31:0]avs_datewrite,
input avs_address,
output reg[31:0]date_k
);
reg wr_n;
always@(avs_address)  begin
 wr_n<=1'b1;
 case(avs_address)
  1'b1:wr_n<=1'b0;
  default:wr_n<=1'b1;
 endcase
end
always@(posedge clk,negedge rst_n)  begin
 if(!rst_n)
  date_k<=32'd0;
 else
  if((!wr_n)&&(!avs_wr_n))
   date_k<=avs_datewrite;
end
endmodule
